Electronic circuit for detecting and evaluating angular acceleration and deceleration of a rotary member

ABSTRACT

An electronic circuit for developing a voltage signal that is proportional in magnitude to the acceleration or deceleration of a rotary member, including a speed pick-up signal generator connected to the rotary member and having an output signal in the form of voltage pulses, a plurality of voltage storage counters, each being connected to an output signal amplifier circuit, a separate electronic gate for controlling the entry of a triggering voltage signal to each of said storage counters and a multi-vibrator switching circuit connecting the input side of each gate with the output side of said speed pick-up whereby the signal generated by said speed pick-up is selectively distributed to the gates to allow each storage counter to develop an output signal voltage that is determined by the number of pulses generated by said pick-up within a predetermined interval, the differences in voltages stored by each counter thereby being a measure of the change in velocity of said rotary member during operation in one interval relative to the speed of the rotary member during operation in another interval.

United States Patent Berry et al.

ELECTRONIC CIRCUIT FOR DETECTING AND EVALUATING ANGULAR ACCELERATION ANDDECELERATION OF A ROTARY MEMBER Inventors: James 1. Berry, Livonia;Zbigniew J.

Jania, Northville, both of Mich.

Assignee: Ford Motor Company, Dearbom, Mich.

Filed: Jan. 19, 1970 Appl. No.: 3,667

us. c1. ..324/162, 188/181 A 1111. c1. ..G0lp 3/42 Field of Search..324/16 1., 78 R, 78 D, 78 2; 307 132, 140, 141; 340/262; 235/92 A,151.32,

150.3, 150.31, 150.2; 303/21 c, 21 BB, 21 co, 21 ce; 188/181 AReferences Cited FOREIGN PATENTS OR APPLICATIONS Great Britain ..324/162 Primary Examiner-Michael J. Lynch Attorney-John R. Faulkner andDonald J Harrington ABSTRACT An electronic circuit for developing avoltage signal that is proportional in magnitude to the acceleration ordeceleration of a rotary member, including a speed pick-up signalgenerator connected to the rotary member and having an output signal inthe form of voltage pulses, a plurality of voltage storage counters,each being connected to an output signal amplifier circuit, a separateelectronic gate for controlling the entry of a triggering voltage signalto each of said storage counters and a multi-vibrator switching circuitconnecting the input side of each gate with the output side of saidspeed pickup whereby the signal generated by said speed pick-up isselectively distributed to the gates to allow each storage counter todevelop an output signal voltage that is determined by the number ofpulses generated by said pick-up within a predetermined interval, thedifferences in voltages stored by each counter thereby being a measureof the change in velocity of said rotary member during operation in oneinterval relative to the speed of the rotary member during operation inanother interval.

8 Claims, 5 Drawing Figures PATENTED I' 6 I972 3,668,524

7F 7re 6 I (Z I C 5}! I cg; I? 54) 0/;ij/ Q; I 0 4%. an I 4 T Z;j pi!)It I: I I I 650 I I I I ELECTRONIC CIRCUIT FOR DETECTING AND EVALUATINGANGULAR ACCELERATION AND DECELERATION OF A ROTARY MEMBER GENERALDESCRIPTION OF THE INVENTION Our invention is adapted especially to beused in antidkid brake systems for wheeled vehicles having individualwheel brakes. It may be used in such an environment to detect angulardeceleration of one of the vehicle wheels. The antiskid brake systemuses this signal, together with an appropriate vehicle speed signal anda wheel brake pressure signal, to control or modulate the magnitude of awheel braking force in order that wheel slippage at the wheel-roadinterface will not exceed a predetermined design value. My invention canbe used in other circuitry, however, where angular acceleration ordeceleration parameters are desired.

The acceleration or deceleration signals that are produced depends uponthe frequency of voltage pulses .developed by a reluctance voltagepick-up device drivably connected to a rotary member. In the case of anantiskid brake system, the rotary member would be the vehicle wheel tobe controlled. An astable multi-vibrator of a predetermined, constantfrequency develops pulse signals of square wave form which are directedto each of a pair of electronic gates. The same gates receive thevoltage pulses from the reluctance pick-up. The output side of each gatereceives voltage pulses when the multivibrator output is in theso-called l state and the output side of the gate is isolated from thereluctance pick-up when the associated signal from the multivibrator isin the state. The output from each of these gates is distributed to eachof two pairs of similar gates. The other input signal for each of thesegates is received from a flip-flop circuitthat is triggered by one ofthe voltage signals from the multivibrator. One side of the flip-flopcircuit is connected to one of a pair of other gates, and the other sideof the flip-flop circuit is connected to the other pair of the othergates. Each of these other gates in turn forms an input signal sourcefor a separate one of four storage counters.

The gate circuit causes the storage counters to be selectively triggeredso that each counter functions during one-quarter of the total timerequired for one complete cycle of the vibrator. The ultimate source foreach of the storage counters is the reluctance pick-up. Thus the voltagedeveloped in each counter during the portion of the operating cycle inwhich it is operational is determined by the number of pulses developedby the reluctance pick-up during that time portion, which in turn is anindicator of the instantaneous angular velocity of the rotary member. Bycomparing the voltage developed in one storage counter with the voltagedeveloped in the next storage counter that is operational in thesequence, an indication of the change of velocity is detected. This isuseful as an indication of acceleration or deceleration.

As the next pair of voltage counters becomes operational, the first pairof voltage counters is deactivated and .conditioned for a subsequentreluctance pick-up voltage pulse count as the operating cycle isrepeated.

DESCRIPTION OF THE FIGURES OF THE DRAWING FIG. 1 shows a schematicelectronic circuit embodying the elements of my invention.

FIG. 2 shows in schematic form an astable multivibrator capable of beingused in the circuit of FIG. 1.

FIG. 3 shows a flip-flop bistable multivibrator capable of being used inthe circuit of FIG. 1.

FIG. 4 shows in schematic form a so-called not and" gate for use in thecircuit of FIG. 1.

FIG. 5 shows the signal voltage wave forms developed by the astablemultivibrator of FIG. 2 and the bistable multivibrator of FIG. 3.

PARTICULAR DESCRIPTION OF THE INVENTION FIG. 1 shows at a toothed discwhich is driven by a driven member. As indicated earlier, this drivenmember may be the road wheel of a wheeled vehicle. The teeth on the disc10 pass through the inductance field of an inductance coil 12 therebycausing voltage pulses in lead 14. The frequency of the pulses generatedby the instantaneous changes in the reluctance of the coil 12 is relateddirectly to the speed of rotation of the disc 10. These voltage pulsesare amplified by a conventional amplifier subcircuit 16 to produce auseful output signal at point 18 on its output side. Point 18 isconnected to the input side of a first gate 20 as well as to the inputside of a second gate 22.

An astable multivibrator 24 produces voltage pulses at each of its twooutput sides. One output side is connected to the gate 22 through line26 and the other output side is connected to the gate 20 through line28. Line 26 receives gate signal G, from one side of the multivibrator24 and line 28 receives a second gate signal G, from the other side ofthe multivibrator 24.

For purposes of illustration, one form of multivibrator that would beuseful in the circuit of FIG. I is shown in FIG. 2. It includes two PNPtransistors Q, and Q, having a common emitter circuit. The Q, is coupledto the base or input side B of the Q, stage. The voltage drop across Rin FIG. 2 can be used as one of the voltage output signals such as 6,.The voltage drop across resistor R in FIG. 2 can be used as the outputvoltage signal for the other stage. This may be the gate signal Line 30in FIG. 1 forms a supply line and is connected to a voltage source Ethrough a suitable switch S. It will be assumed that the characteristicsof the transistors are such that transistor Q, conducts more readilythan does 0 The collector voltage at point 32 for the transistor Q, thenfalls to a value that is lower than the corresponding value at point 34for the transistor 0,. Capacitor C which couples the input for the Qstage to the output side of the Q, stage, then discharges through thecollector-emitter circuit for 0,, which circuit includes the resistor RThis places a reverse bias on the baseemitter circuit for 0,, therebycausing Q to be non-conductive.

Capacitor C, at this time becomes charged by the base emitter-circuitfor Q, and resistor R thereby adding forward bias current to the Q,input. This causes Q, to reach its saturation level.

The voltage on capacitor C falls ofi as it continues to discharge andthe base voltage bias for 0, becomes less positive. When the bias on Qreaches zero, 0, forward bias current begins to flow from the voltagesource E through resistor R This causes the collector circuit for O toconduct. As this occurs, the voltage at point 34 falls and capacitor C,discharges through the collector-emitter circuit for Q and resistor R,.This flow of current,due to the discharge of capacitor C,,places areverse bias on the base-emitter circuit of Q, causing it to stopconducting. Capacitor C, then recharges by virtue of its connection withthe base-emitter circuit of Q and the connection through R The rechargedcapacitor C increases the forward bias on the 0, input. This then causesthe transistor 0, to reach its saturation level.

This process continues, thereby producing square wave voltage pulses inalternate sequence. These pulses are indicated by the symbols G, and Gin FIG. 1. They are graphically represented in charts 36 and 38 of FIG.5. It is seen that when the signal G, goes from the 0 state to the Istate, the signal 6, goes from the represented 1" state to the 0" state.Conversely, when signal G, goes from the 0" state to the l state, thesignal G, goes from the l state to the 0 state. Time is plotted in thecharts of FIG. 5 along the abscissa and voltages are plotted along theordinate.

The astable multivibrator 24 serves as a switching circuit for the gates20 and 22. For the purpose of indicating the function of these gates 20and 22, reference may be made to FIG. 4 where gate 20 is illustrated inschematic form. The other gates may be duplicates of this.

The output signal G, for the astable multivibrator 24 is distributed togate 20 through line 28, but for the purposes of FIG. 4 the voltagepulses may be thought of as the result of opening and closing amechanical switch shown at 24'. In a similar fashion the output signalfrom the reluctance pick-up is distributed to the gate 20 through line30, but for purposes of FIG. 4 the voltage pulses may be thought of asbeing established by opening and closing a second mechanical switch 16'.

A common side for each of the switches is grounded as shown at 32. Theother terminal of switch 24' is connected to the output side of a firstdiode 34. Similarly, the other terminal of the switch 16' is connectedto the output side of a second diode 36.

An NPN transistor 38 is connected at its base to the input sides of thediodes 34 and 36. The base also is connected to supply line 40 throughresistor 42. The collector circuit for the transistor 38 is connected tothe supply line 40 through resistor 44.

Whenever switch 24' is in the state, current will flow from line 40through resistor 42 producing a voltage drop across the resistor. Thecurrent flows then through diode 34 and switch 24' to the ground. Thereis no base-emitter voltage bias across transistor 38 at this timebecause of the voltage drop across resistor 42. Thus there is no currentin resistor 44 and the output voltage measured at point 46 is zero.Switch 16' can move between the 0" state and the l state without havingany influence on the output voltage at point 46.

If switch 24' should move to the 1 state and switch 16 should move tothe 0 state, there again will be a reverse bias on the transistor 38,thereby preventing a voltage signal at point 36 from developing. If theswitch 16 should move to the l state, current flow through resistor 42is interrupted and the base-emitter voltage increases, therebytriggering the transistor 38 and producing a voltage drop acrossresistor 44. This causes a voltage signal at point 46 to be developed.That voltage signal, however, is in the opposite direction from thesignal direction for the supply lines. It is seen, therefore, that ifeither switch is in the 0 state, the output voltage at point 46 is zero.If one of the switches is in the l state and the other switch movesbetween the 0" state and the "1 state, the voltage signal at point 46will move between the 1 state and the 0 state as the sign of the voltagesignal is reversed. It is seen, therefore, that whenever the astablemultivibrator 24 develops a signal (3,, which would correspond tomovement of switch 24 to the l state, voltage pulses are established bythe inductance pick-up 16, which would correspond to the rapid movementof switch 16 between the "0 state and the l state. The output voltagemeasured at point 46 will be a pulsating voltage of the same frequencybut of opposite sign from the voltage pulses developed by the reluctancepick-up 16. The voltages pulses of the pick-up 16 are not transmittedthrough the gate, however, when the astable multivibrator 24 does notdevelop a signal G,.

The operation of the gate 22 in response to the signal C i, is the sameas that previously described with respect to gate and the signal 6,. Inother words, gate 22 will distribute the voltage pulses of pick-up 16only when the signal 6, is available.

Signal G, is the input signal for the flip-flop bistable multivibrator48. This is shown in detail in FIG. 3. The circuit of FIG. 3 includestwo transistors Q, and Q of the PNP type. The collector circuit for eachtransistor is supplied with voltage from a common line 50 which has anegative potential. The input signal G, is applied to the bases oftransistors Q, and Q The output signals for the bistable multivibrator48 are G, and G These are measured across resistors R, and Rrespectively. These are located in the collector circuits for thetransistor Q, and Q respectively.

in the circuit of FIG. 3, Q, conducts when 0, is turned off and Q, isturned off when Q conducts. The change from one condition to the otheris triggered by the voltage pulse G,.

if it is assumed at the outset that no voltage signal G, is present, andif it is assumed that transistor 0, conducts current more readily thantransistor Q voltage signal G, will result because of the voltage dropacross resistor R This voltage drop reduces the voltage applied to thedivider circuit shown at R,,, R, and voltage source E,,. This voltagesource has a potential that is greater than the voltage drop acrossresistor R Thus a reverse bias is applied to the base of the transistor48, and current through the collector circuit for the transistor 48 iscut off. Voltage is measured at that point. Signal G, thus rises to avalue almost equal to the voltage in line 50. This results in anincreased voltage across the divider R, and R,. The voltage drop acrossR, exceeds the voltage E thus placing a forward bias on the Q,base-emitter circuit. Transistor Q, thus conducts heavily at itssaturation level. This is a stable condition which will not be changedunless the stability is upset. The equilibrium is upset by theapplication of signal G, to the base of the transistor 0,. if it isassumed that this pulse is positive, the current in R, is reduced andthe collector current in transistor Q, also is reduced. Voltage Gincreases because of the smaller voltage drop across R and the voltagesupplied to the divider R and R increases. This results in a forwardbias on the transistor Q causing collector current in transistor Q, toincrease. The voltage signal 5, falls due to the increased current in R,and less voltage then is applied to the dividerR, and R,. The voltagedrop across R, thus falls below E and Q, is cut off. This also is astable condition which will continue as long as the voltage pulse G,continues.

The signal G developed by the bistable multivibrator 48 is distributedto gate 52 and to gate 54. The signal G is distributed to gates 56 and58.

Gates 52 and 56 receive a second input signal from gate 22, and gates 54and 58 receive a second input signal from the gate 20. Each of the gates52, 56, 54 and 58 operates in the same manner as the gate 20 which wasdescribed with reference to FIG. 4. The output side of each gate 52, 56,54 and 58 is connected to the input side of a separate voltage storagecounter as indicated, respectively, at 60, 62, 64 and 66.

The frequency of the output signal for the bistable multivibrator 48 isexactly one-half of the frequency of its input signal. Thus for eachpulse of the 0, signal, for example, two pulses for the input signal arerequired. The same is true for the output signal G The relationshipbetween the wave forms for each of the four signals 6,, G,, G and G isillustrated in FIG. 5 where voltage is plotted on the ordinate and timeis plotted on the abscissa.

The output side of each gate 52, 56, 54 and 58 will be conditioned toreceive selectively the voltage pulses supplied by the reluctancepick-up 10. During the time in which the gate for any particular storagecounter is open, the storage counter receives the voltage pulses andstores them in its internal capacitance. This develops an output signalvoltage which is a measure of the average velocity of the driven memberduring the interval in which the gate is open. The timing of the gates,of course, is fixed at a constant value determined by the frequencyinherent in the astable multivibrator 24.

Since the storage counters are identical, only one of them, namelycounter 60, will be described here.

The capacitor 68 has one side connected to the output side of the gate52. It receives pulses from the reluctance pick-up when both G, and Gare in the l state. Similarly, because of the action of the gate 54,storage counter 64 will receive pulses only when both G, and G are inthe 1 state. When G, goes to the 0 state, gate 54 is closed, asexplained previously. Similarly, if (T, goes to the 0" state, gate 52 isclosed, as explained previously.

Because the frequency of the pulses G and G: are exactly one-half thefrequency of the pulse in G, and GI, gate 52 will be opened during thefirst one-half of the time 0,. is in the l state and gate 54 will beopened during the last one-half of the time in which G is in the lstate. it is apparent, therefore, that both the storage counters 60 and64, at the end of the time in which G is in the l state, will havestored a voltage charge. If the speed of rotation of the driven memberassociated with the reluctance pick-up does not change, those storedvoltages will be the same. If a speed change occurs during the time inwhich G remains in the l state, the voltages stored by counters 60 and64 will be different.

The voltage charge developed by a single impulse distributed through thegate 52 is transferred through a rectifying diode 70 to one side ofstorage capacitor 72. The other side of capacitor 72 is grounded. Thisproduces a base-emitter voltage bias on NPN transistor 74 which causes acollector current to flow through resistor 76.

A switching transistor 78 and the transistor 74 have a common emittercircuit. The collector circuit for the transistor 78 is connected to theinput side of an output amplifier 80. The base of the transistor 78receives the signal 6, through line 82. The voltage drop across resistor76, because of the forward bias imparted to the base-emitter circuit fortransistor 74, will not produce a forward bias on the transistor 78because signal G is applied to the base for the transistor 78. Thissignal exceeds the voltage drop across resistor 76.

Diode 70 allows transfer of the pulse signals received by the capacitor68 to the storage capacitor 72, thereby developing in steps a voltagepotential. This potential is not dissipated, however, until the gatesignal G assumes a state, thereby removing the reverse bias on thetransistor 78.

The same signal G that kept transistor 78 from conducting is applied tothe base for transistor 84 on the output side of the storage counter 64.The base for transistor 84 is connected to the signal source for Gthrough line 86.

As mentioned earlier, both counters 60 and 64 develop charges during thetime in which the signal G is present. As soon as the signal G assumesthe 0" state, both transistors 84 and 78 begin to conduct, therebydistributing the signals from counters 60 and 64 simultaneously to theamplifier 80.

The storage voltage represented by the symbol V is distributed to theamplifier 80 at one input point 86 and the input storage voltage V forthe counter 64 is distributed to themplifier 80 at input point. Theamplifier 80 substracts the voltage values and amplifies thedifferential voltage to produce a resultant voltage E which is a measureof the change in velocity that occurs during the time required tocomplete onehalf cycle for the bistable multivibrator 48.

The capacitor 72, which induced the signal that was received by theamplifier 80 is discharged by a capacitor bypass passage defined bytransistor 90. Whenever a signal G is present, the base for transistor90 receives a reverse bias which prevents collector current from flowingthrough the transistor 90 around the capacitor 72. After the signal Gassumes a 0 state and the collector 60 distributes its stored voltagesignal to the amplifier 80, the potential existing across capacitor 78is dissipated through the collector circuit for the transistor 90.

A rectifying diode 92 is interposed between one side of the capacitor 70and output side of the capacitor 68. As capacitor 68 receives at itsinput side the pulses during the time that G is in the 1" state, thepulses themselves will oscillate back and forth between the l state andthe 0" state. As soon as a pulse assumes the l state, capacitor 68begins to discharge through diode 70 to the storage capacitor 72. Whenthe pulse goes to the 0 state, thecharge on capacitor 68 will be lessthan it was during the initiation of the l state for the preced ingpulse. In order to prevent the output side of the capacitor 68 fromassuming a negative charge when the pulse itself assumes the 0" state,the diode will provide a connection with ground. This will preventreduction of the charge on the output side of the capacitor 68 to apotential less than zero.

The counters 62 and 66 have suitable switching transistors 91, 92, 94and 96, respectively. These correspond to the switching transistorspreviously described for the counters 60 and 64.

Storage counters 60 and 64 are discharged when G goes from the 0" stateto the 1 state, as explained previously. In a similar fashion storagecounters 62 and 66 are discharged when G goes from the 0" state to the lstate.

Each storage counter receives pulses for one-quarter of the period ofthe astable multivibrator 24 or one-half of the period for the bistablemultivibrator 48. Storage counter 60 receives pulses when both 5, and Gare in the l state, as explained previously. Similarly, storage counter64 receives pulses when both G and G are in the l state. Storage counter62 receives pulses when both G, and G are in the "1" state. Storagecounter 66 receives pulses when both G, and G are in the 1 state.

The storage counters are charged in the sequence 60, 64, 62 and 66.

The amplifier substracts the voltage output of counter 60 from thevoltage output of counter 64 when G, is in the 0" state. Amplifier 80substracts the voltage output of counter 60 from the voltage output ofcounter 64 when G is in the 0 state. Amplifier 80 substracts the voltageoutput of counter 62 from the voltage output of counter 66 when (T; isin the 0 state. One of these pairs of counters is in condition foraccumulating voltages when the storage capacitors for the other pair ofcounters is being erased or dissipated prior to a subsequent voltageaccumulation as the previously described cycle is repeated. The averagevoltage E, at any instant thus provides an instantaneous reading of theacceleration of the rotary member.

Having thus described a preferred fon'n of our invention, what we claimand desire to secure by US. Letters Patent is:

1. An angular accelerometer adapted to measure the angular accelerationof a rotary member comprising a velocity pick-up means for developingvoltage pulses having a frequency that is proportional in magnitude tothe rotary speed of said member, an astable multivibrator circuit meansfor developing voltage pulses at each .of two output sides thereof, abistable vibrator circuit means for developing in alternating sequencetwo additional voltage pulses, two electrical gates each having twoinput terminals and one output terminal, a separate one of the outputsides of said astable multivibrator circuit means being connected to oneinput terminal of each of said gates, four additional gates, each havinga pair of input terminals and a single output terminal, one inputterminal of each of a first pair of said four additional gates beingconnected to the output side of one of said first mentioned gates, asecond pair of said four additional gates having an input terminalconnected to the output terminal of the other of said first mentionedgates, a first output side of said bistable multivibrator circuit meansbeing connected to one terminal of one of said first pair of gates andto one terminal of said second pair of gates and the second side thereofbeing connected to one terminal of one of the other of said one pair ofgates and to one terminal of one of the other of said other pair ofgates, four storage voltage counters, a separate one of a first pair ofsaid counters being connected to the output terminal of each of saidfirst pair of said four additional gates, a separate one of a secondpair of said counters being connected to the output terminal of each ofsaid second pair of said four additional gates, one storage counter ofeach of said pair of storage counters being connected through theirrespective gates to a first output side of said bistable multivibratorcircuit means whereby they accumulate voltage charges when a signal isavailable from said bistable multivibrator circuit means, the secondoutput side of said bistable multivibrator circuit means being connectedto the other of each of said pairs of storage counters through theirrespective gates, said counters accumulating voltage charges when asignal is available from said bistable multivibrator circuit means,means for comparing the voltage charges accumulated by a storage counterof said first pair of storage counters and by a storage counter of saidsecond pair of storage counters during one-half of the complete periodof the oscillation of said astable multivibrator circuit means and meansfor comparing the accumulated voltages in the other storage counters ofeach pair during the other half of the period of vibration of saidastable multivibrator circuit means whereby the average voltagedifferential so compared indicates the change in speed of said drivenmember during one interval.

2. The combination as set forth in claim 1 wherein each of said gatesestablishes a voltage pulse distribution circuit therethrough when thevoltage pulse applied to its other input terminal is present, saiddistribution circuit being interrupted by said gate in response to aloss of the voltage pulse on said other input terminal.

3. The combination as set forth in claim 1 wherein said means forcomparing the accumulated voltages in said storage counters comprises anoutput amplifier circuit having two input terminals and one outputterminal, each of the input terminals being connected to a separate pairof storage counters whereby the output terminal is subjected to avoltage potential that is proportional to the difference in the voltagepotentials supplied to the input terminals of the output amplifiercircuit.

4. The combination as set forth in claim 2 wherein said means forcomparing the accumulated voltages in said storage counters comprises anoutput amplifier circuit having two input terminals and one outputterminal, each of the input terminals being connected to a separate pairstorage counter whereby the output terminal is subjected to a voltagepotential that is proportional to the difference in the voltagepotentials supplied to the input terminals of the output amplifiercircuit.

5. The combination as set forth in claim 1 wherein each storage countercomprises a storage capacitor, a charge dissipating circuit bypassingsaid capacitor, said bypass circuit being connected to the gate terminalassociated with said storage counter that is subjected to a voltage ofknown frequency, the negative bias produced on said bypass circuit beingdissipated when said storage counter registers its output signal,thereby conditioning said storage capacitor for a voltage accumulationmode as the voltage storing cycle is repeated.

6. The combination as set forth in claim 2 wherein each storage countercomprises a storage capacitor, a charge dis sipating circuit bypassingsaid capacitor, said bypass circuit being connected to the gate terminalassociated with said storage counter that is subjected to a voltage ofknown frequency, the negative bias produced on said bypass circuit beingdissipated when said storage counter registers its output signal,thereby conditioning said storage capacitor for a voltage accumulationmode as the voltage storing cycle is repeated.

7. The combination as set forth in claim 3 wherein the bistablemultivibrator circuit means has a single input which triggers a voltageimpulse at each output side thereof in alternating sequence, said inputside being connected to one of the output terminals of saidfirst-mentioned multivibrator circuit means whereby the oscillatingfrequency of said bistable multivibrator circuit means is one-half ofthe vibrating frequency of said first-mentioned multivibrator circuitmeans.

8. The combination as set forth in claim 4 wherein the bistablemultivibrator circuit means has a single input which triggers a voltageimpulse at each output side thereof in alternating sequence, said inputside being connected to one of the output terminals of saidfirst-mentioned multivibrator circuit means whereby the oscillatingfrequency of said bistable multivibrator circuit means in one-half ofthe vibrating frequency of said first-mentioned multivibrator circuitmeans.

1. An angular accelerometer adapted to measure the angular accelerationof a rotary member comprising a velocity pick-up means for developingvoltage pulses having a frequency that is proportional in magnitude tothe rotary speed of said member, an astable multivibrator circuit meansfor developing voltage pulses at each of two output sides thereof, abistable vibrator circuit means for developing in alternating sequencetwo additional voltage pulses, two electrical gates each having twoinput terminals and one output terminal, a separate one of the outputsides of said astable multivibrator circuit means being connected to oneinput terminal of each of said gates, four additional gates, each havinga pair of input terminals and a single output terminal, one inputterminal of each of a first pair of said four additional gates beingconnected to the output side of one of said first mentioned gates, asecond pair of said four additional gates having an input terminalconnected to the output terminal of the other of said first mentionedgates, a first output side of said bistable multivibrator circuit meansbeing connected to one terminal of one of said first pair of gates andto one terminal of said second pair of gates and the second side thereofbeing connected to one terminal of one of the other of said one pair ofgates and to one terminal of one of the other of said other pair ofgates, four storage voltage counters, a separate one of a first pair ofsaid counters being connected to the output terminal of each of saidfirst pair of said four additional gates, a separate one of a secondpair of said counters being connected to the output terminal of each ofsaid second pair of said four additional gates, one storage counter ofeach of said pair of storage counters being connected through theirrespective gates to a first output side of said bistable multivibratorcircuit means whereby they accumulate voltage charges when a signal isavailable from said bistable multivibrator circuit means, the secondoutput side of said bistable multivibrator circuit means being connectedto the other of each of said pairs of storage counters through theirrespective gates, said counters accumulating voltage charges when asignal is available from said bistable multivibrator circuit means,means for comparing the voltage charges accumulated by a storage counterof said first pair of storage counters and by a storage counter of saidsecond pair of storage counters during one-half of the complete periodof the oscillation of said astable multivibrator circuit means and meansfor comparing the accumulated voltages in the other storage counters ofeach pair during the other half of the period of vibration of saidastable multivibrator circuit means whereby the average voltagedifferential so compared indicates the change in speed of said drivenmember during one interval.
 2. The combination as set forth in claim 1wherein each of said gates establishes a voltage pulse distributioncircuit therethrough when the voltage pulse applied to its other inputterminal is present, said distribution circuit being interrupted by saidgate in response to a loss of the voltage pulse on said other inputterminal.
 3. The combination as set forth in claim 1 wherein said meansfor comparing the accumulated voltages in said storage counterscomprises an output amplifier circuit having two input terminals and oneoutput terminal, each of the input terminals being connected to aseparate pair of storage counters whereby the output terminal issubjected to a voltage potential that is proportional to the differencein the voltage potentials supplied to the input terminals of the outputamplifier circuit.
 4. The combination as set forth in claim 2 whereinsaid means for comparing the accumulated voltages in said storagecounters comprises an output amplifier circuit having two inputterminals and one output terminal, each of the input terminals beingconnected to a separate pair storage counter whereby the output terminalis subjected to a voltage potential that is proportional to thedifference in the voltage potentials supplied to the input terminals ofthe output amplifier circuit.
 5. The combination as set forth in claim 1wherein each storage counter comprises a storage capacitor, a chargedissipating circuit bypassing said capacitor, said bypass circuit beingconnected to the gate terminal associated with said storage counter thatis subjected to a voltage of known frequency, the negative bias producedon said bypass circuit being dissipated when said storage counterregisters its output signal, thereby conditioning said storage capacitorfor a voltage accumulation mode as the voltage storing cycle isrepeated.
 6. The combination as set forth in claim 2 wherein eachstorage counter comprises a storage capacitor, a charge dissipatingcircuit bypassing said capacitor, said bypass circuit being connected tothe gate terminal associated with said storage counter that is subjectedto a voltage of known frequency, the negative bias produced on saidbypass circuit being dissipated when said storage counter registers itsoutput signal, thereby conditioning said storage capacitor for a voltageaccumulation mode as the voltage storing cycle is repeated.
 7. Thecombination as set forth in claim 3 wherein the bistable multivibratorcircuit means has a single input which triggers a voltage impulse ateach output side thereof in alternating sequence, said input side beingconnected to one of the output terminals of said first-mentionedmultivibrator circuit means whereby the oscillating frequency of saidbistable multivibrator circuit means is one-half of the vibratingfrequency of said first-mentioned multivibrator circuit means.
 8. Thecombination as set forth in claim 4 wherein the bistable multivibratorcircuit means has a single input which triggers a voltage impulse ateach output side thereof in alternating sequence, said input side beingconnected to one of the output terminals of said first-mentionedmultivibrator circuit means whereby the oscillating frequency of saidbistable multivibrator circuit means in one-half of the vibratingfrequency of said first-mentioned multivibrator circuit means.